Architectural Design of Neural Network Hardware for Job Shop Scheduling

By combining neural network optimization ideas with “Lagrangian relaxation” for constraint handling, a novel Lagrangian relaxation neural network (LRNN) has recently been developed for job shop scheduling. This paper is to explore architectural design issues for the hardware implementation of such neural networks. A digital circuitry with a micro-controller and an optimization chip is designed, where a parallel architecture and a pipeline architecture are explored for the optimization chip. Simulation results show that the LRNN hardware will provide near-optimal solutions for practical job shop scheduling problems. It is estimated that the parallel architecture will obtain one order of magnitude speed gain, and the pipeline architecture will obtain two orders speed gain as compared with the currently used method.